errata/332: 12.3.3 -- port direction declarations that don't mention the size of port

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Tue Apr 15 2003 - 16:40:48 PDT

  • Next message: Clifford E. Cummings: "Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port"

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    >Number: 332
    >Category: errata
    >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
    >Environment:
    >Description:

    Is the following legal? --

      module m (out, in) ;

      output out ;
      reg [7:0] out ;

      input in ;
      wire [7:0] in ;

      always @(in) out = in ;

      endmodule

    There are no examples like this in the LRM, and it seems OK to me,
    but it almost runs afoul of this sentence in 12.3.3 --

      "If the net or variable is declared as a vector, the range
       specification between the two declarations of a port shall
       be identical."

    I don't know what is meant by 'between' here, but in the code example,
    only the reg or wire declarations include a range specification, so
    there's nothing to be identical with.

    -- Brad

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