From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Tue Apr 15 2003 - 17:10:01 PDT
Precedence: bulk
The following reply was made to PR errata/332; it has been noted by GNATS.
From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
To: etf-bugs@boyd.com
Cc:
Subject: Re: errata/332: 12.3.3 -- port direction declarations that
don't mention the size of port
Date: Tue, 15 Apr 2003 17:02:36 -0700
Hi, Brad -
This is a Verilog-1995 style module header so both the output and reg must
be declared with the same range and the input and wire (optional) must be
declared with the same range. I believe the sentence is correct as is.
I hate reg declarations! :-)
Regards - Cliff
At 04:40 PM 4/15/03 -0700, Brad Pierce wrote:
>Precedence: bulk
>
>
> >Number: 332
> >Category: errata
> >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
> >Environment:
> >Description:
>
>Is the following legal? --
>
> module m (out, in) ;
>
> output out ;
> reg [7:0] out ;
>
> input in ;
> wire [7:0] in ;
>
> always @(in) out = in ;
>
> endmodule
>
>There are no examples like this in the LRM, and it seems OK to me,
>but it almost runs afoul of this sentence in 12.3.3 --
>
> "If the net or variable is declared as a vector, the range
> specification between the two declarations of a port shall
> be identical."
>
>I don't know what is meant by 'between' here, but in the code example,
>only the reg or wire declarations include a range specification, so
>there's nothing to be identical with.
>
>-- Brad
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
This archive was generated by hypermail 2.1.4
: Tue Apr 15 2003 - 17:10:51 PDT
and
sponsored by Boyd Technology, Inc.