From: Shalom.Bresticker@motorola.com
Date: Tue Apr 15 2003 - 20:50:02 PDT
Precedence: bulk
The following reply was made to PR errata/332; it has been noted by GNATS.
From: Shalom.Bresticker@motorola.com
To: etf-bugs@boyd.com
Cc:
Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't
mention the size of port
Date: Wed, 16 Apr 2003 06:44:59 +0300 (IDT)
To clarify, at least as I understand it:
The example is ILLEGAL.
"output out ;" implicitly declares it as a scalar.
It does "run afoul of 12.3.3".
"between the two declarations" means that the same range needs to appear in both
the wire/reg declaration and the port declaration.
If it is unclear, then the text should be reworded.
Shalom
> This is a Verilog-1995 style module header so both the output and reg must
> be declared with the same range and the input and wire (optional) must be
> declared with the same range. I believe the sentence is correct as is.
>
> >Is the following legal? --
> >
> > module m (out, in) ;
> >
> > output out ;
> > reg [7:0] out ;
> >
> > input in ;
> > wire [7:0] in ;
> >
> > always @(in) out = in ;
> >
> > endmodule
> >
> >There are no examples like this in the LRM, and it seems OK to me,
> >but it almost runs afoul of this sentence in 12.3.3 --
> >
> > "If the net or variable is declared as a vector, the range
> > specification between the two declarations of a port shall
> > be identical."
> >
> >I don't know what is meant by 'between' here, but in the code example,
> >only the reg or wire declarations include a range specification, so
> >there's nothing to be identical with.
--
Shalom Bresticker Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
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