errata/338: syntax of edge sensitive module path descriptions

From: Dennis Marsa (drm@xilinx.com)
Date: Tue Apr 29 2003 - 15:43:47 PDT

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    >Number: 338
    >Category: errata
    >Originator: Dennis Marsa <drm@xilinx.com>
    >Environment:
    >Description:

    In 1364-1995, the syntax for edge sensitive module path
    descriptions is described by the following BNF rules
    in A.7, and in syntax box 13-5.

       parallel_edge_sensitive_path_description ::=
           "(" [ edge_identifier ] specify_input_terminal_descriptor "=>"
                specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")"
    ")"

       full_edge_sensitive_path_description ::=
           "(" [ edge_identifier ] list_of_path_inputs "*>"
                list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" ")"

    In 1364-2001, the syntax for edge sensitive module path
    descriptions was changed to the following (in A.7.4, and
    in syntax box 14-4):

       parallel_edge_sensitive_path_description ::=
           "(" [ edge_identifier ] specify_input_terminal_descriptor "=>"
                specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression ")"

       full_edge_sensitive_path_description ::=
           "(" [ edge_identifier ] list_of_path_inputs "*>"
                list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")"

    The difference is that the closing ")" was removed in each rule. In the 1364-1995
    syntax there is one opening "(" and two closing ")", so they are not balanced. In
    1364-2001 they are now balanced.

    Does 1364-2001 indicate the proper syntax?

    Perhaps not. Verilog-XL, NC-Verilog, and MTI all seem to want to parse the following
    third syntax for edge sensitive module path descriptions:

       parallel_edge_sensitive_path_description ::=
           "(" [ edge_identifier ] specify_input_terminal_descriptor "=>"
                "(" specify_output_terminal_descriptor [ polarity_operator ] ":" data_source_expression
    ")" ")"

       full_edge_sensitive_path_description ::=
           "(" [ edge_identifier ] list_of_path_inputs "*>"
                "(" list_of_path_outputs [ polarity_operator ] ":" data_source_expression ")" ")"

    The difference between the 1364-1995 syntax and the above is the *addition* of a second
    opening "(" before the outputs.

    Here is a concrete example showing each of the above three syntaxes.

      specify
         ( posedge in => out : data ) ) = 1; // 1364-1995 syntax
         ( posedge in => out : data ) = 1; // 1364-2001 syntax
         ( posedge in => ( out : data ) ) = 1; // syntax required by Verilog-XL, NC-Verilog and MTI
      endspecify

    Dennis Marsa
    Xilinx, Inc.

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