From: James A. Markevitch (jam@magic.com)
Date: Mon May 05 2003 - 08:25:12 PDT
Precedence: bulk
>Number: 340
>Category: errata
>Originator: "James A. Markevitch" <jam@magic.com>
>Environment:
>Description:
Proposal: reject the comment
Although it might have made sense to allow anonymous module instantiation
when Verilog was a new language, at this point the impact of making such a
change is probably substantial.
As has been pointed out from the e-mail thread on this topic, instance
names for instantiated modules are valuable in their use of examining the
hierarchy below that instantiation. Adding the notion of anonymous module
instantiation would result in: loss of the ability to inspect the contents
of such an instatiation; and/or, loss of PLI access to such a module; and/or
the requirement to specify how such access could be restored.
James Markevitch
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