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From: Krishna Garlapati (krishna@synplicity.com)
Date: Mon May 05 2003 - 16:19:10 PDT

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    Hi,

      I looked into the new proposed syntax and semantics changes to
    generate statement. The proposal is really good. It addresses almost all
    the thorny issues with  generates. I have a couple of comments.

    1) The proposal to deprecate genvar type needs to be given some more
    thought. We have ton of customers using genvars and I am pretty sure they
    will not be too happy with this. If the only issue with genvars is that the
    definition is too restrictive in the original LRM, how about removing them.
    Allowing genvar type to be assigned a -ve value will remove a major
    restriction.

    The proposal to use local_param's is a good one and makes lots of sense.
    I think both genvar's and local_param's can co-exist and behave identically
    in the scope  of generates.

    2) Scoping and Conditional Rules. This is my biggest issue with generate
    statements in the current form.  I think it would really simplify things if
    the new proposal would instead allow declarations only within  a named
    begin-end block (generate-block with a compulsory : generate_block_identifier
    in the current LRM) This will also make it consistent with the rest of Verilog
    local declarations.

    Also, there are some issue's with implicit nets automatically declared within
    instantiations.  It would be great if there was a clean way to solve references
    (bindings) if these nets were assigned values from within generates. Here is
    a verilog snippet.

    module top;

    wire y,z;

    generate
    if(something_true)
        assign x = 1'b1;
    end generate;

    some_module my_module(x, y, z);

    endmodule

    3) I am not in favor of the proposal to totally get rid of generate-endgenerate
    keywords. Even if the generate-endgenerate pair serve no other purpose
    they help keep the code well structured and easily identifiable ( 95 vs 01)

    Even though our collective intention  here is  to see that there is only
    one Verilog standard, the end users don't think like that (yet).  I have
    seen people asking what if this were in 95 standard Vs 2001.
    generate-endgenerate would keep these guys happy.

    Since  I am new here, excuse me if someone had already brought up these
    issues.

    --
    sig - Krishna. Synplicity, Inc. (408)215-6152

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