From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Fri May 09 2003 - 18:58:55 PDT
>Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
According to 12.3.4, regarding ANSI-style module ports, "Each declared
port provides the complete information about the port." According to
12.3.3, if a port declaration does not include a net or variable type,
then the port can be again declared in a net or variable declaration."
Does this mean that the following is legal? --
module m( input x ) ;
wire x ;
I think it shouldn't be. If the information is complete, then even
redundant declarations should be prohibited.
Are there any restrictions on redeclarations of ANSI-style
task/function ports? I don't see any restrictions in 10.2.1 and
10.3.1. To me it would make sense if each ANSI-style task/function
declaration would provide the complete information about the port
and if it would be illegal to redeclare such ports within the body,
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