Re: enhancement/350: Proposal to deprecate configs in Verilog source files

From: Krishna Garlapati (krishna@synplicity.com)
Date: Tue May 20 2003 - 10:00:02 PDT

  • Next message: Steven Sharp: "Re: enhancement/350: Proposal to deprecate configs in Verilog source files"

    Precedence: bulk

    The following reply was made to PR enhancement/350; it has been noted by GNATS.

    From: Krishna Garlapati <krishna@synplicity.com>
    To: sharp@cadence.com
    Cc: etf-bugs@boyd.com
    Subject: Re: enhancement/350: Proposal to deprecate configs in Verilog source
     files
    Date: Tue, 20 May 2003 09:58:22 -0700

     This is a very neat idea. Seperating link info from source code
     makes most practical sense.
     
     - Krishna.
     
     sharp@cadence.com wrote:
     
    >Precedence: bulk
    >
    >
    >
    >
    >>Number: 350
    >>Category: enhancement
    >>Originator: sharp@cadence.com
    >>Environment:
    >>
    >>
    >
    >
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    >>Description:
    >>
    >>
    >
    >Verilog-2001 allows configs to appear in either Verilog
    >source files, or the library map file. I am proposing
    >that they not be allowed in Verilog source files, only
    >in the library map file.
    >
    >The main reason for proposing this is that configs use
    >a lot of reserved keywords that can create backward
    >compatibility problems for existing designs. A test on
    >a large set of real customer designs indicated that 15%
    >of them would not compile with these keywords reserved.
    >And before anyone suggests context-sensitive keywords
    >(blech!), the main offender was the keyword "config",
    >which marks the start of the context and therefore
    >can't be context-sensitive.
    >
    >The idea of having configs in the source code presumably
    >came from VHDL. Most experienced Verilog people I have
    >consulted agree that Verilog source files should only
    >contain real Verilog source, and that configs should be
    >put in a side file. The existing standard already allows
    >for them to be put into the library map file, which fits
    >that description nicely.
    >
    >Nor is putting configs in the Verilog source file the
    >most beneficial use model. If you want to change what are
    >effectively "link" options, you don't want to have to
    >change and recompile the source code each time. My
    >inquiries indicate that VHDL users most often supply
    >configs in separate files, usually generated by tools
    >and at most tweaked by hand. So this seems to be the
    >most natural way of using them anyway.
    >
    >If we do deprecate this, it would be best to do it
    >soon and publicize it before it comes into wide use.
    >
    >
    >
    >
     
     --
     - Krishna Garlapati, Synplicity Inc. (408)215-6152
     
     

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