Re: errata/364: Preprocessor macros within strings.

From: Steven Sharp (sharp@cadence.com)
Date: Mon Jun 16 2003 - 15:50:06 PDT

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    The following reply was made to PR errata/364; it has been noted by GNATS.

    From: Steven Sharp <sharp@cadence.com>
    To: etf-bugs@boyd.com, mac@verisity.com
    Cc:
    Subject: Re: errata/364: Preprocessor macros within strings.
    Date: Mon, 16 Jun 2003 18:40:13 -0400 (EDT)

    > Macros have always been substituted in strings in Verilog, since time
    > began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where
    > this is documented on page 2-6).
     
     Mac, can you quote the text you are referring to from the 1.1a manual?
     The earliest I have is a 1.6c manual from June 1993, which doesn't say
     anything about it. The OVI 2.0 LRM from March 1993 also doesn't say
     anything about it.
     
     At any rate, a current version of Verilog-XL does not substitute macros
     in strings. This might be a situation where Verilog has evolved since
     time began.
     
     Steven Sharp
     sharp@cadence.com
     

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