Date: Sun Jul 27 2003 - 02:18:30 PDT
4.1.13 ("Conditional operator") says,
"The evaluation of a conditional operator shall begin with
the evaluation of expression1. If expression1 evaluates
to false (0), then expression3 shall be evaluated and used
as the result of the conditional expression. If
expression1 evaluates to true (known value other than 0),
then expression2 is evaluated and used as the
result. If expression1 evaluates to ambiguous value (x or z),
then both expression2 and expression3 shall be
evaluated and their results shall be combined, bit by bit"
The question is, what is meant by
"true (known value other than 0)" and
"ambiguous value (x or z)".
The correct interpretation (according to Verilog-XL, VCS,
and NC-Verilog) is that "2'b1x" is considered "true" even
though it contains x, because it is definitely different
However, someone might interpret "known value" to mean that
all bits are known, and that 2'b1x does not have a "known
value", and that a value is "ambiguous" if it contains any
x or z even if it is definitely different from 0.
This should be clarified.
I bring this up because I saw someone who wrote that ?:
combines expr2 and expr3 if any bits of expr1 are x/z.
I suspect that maybe he thought so because of the wording
of this section.
An example of such a case should be added.
This archive was generated by hypermail 2.1.4
: Sun Jul 27 2003 - 02:20:58 PDT
sponsored by Boyd Technology, Inc.