enhancement/381: ANALYZED - table model system task

From: cranston@cadence.com
Date: Tue Aug 05 2003 - 06:09:12 PDT

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    More info on the reasoning behind this one. Some analog/mixed-signal users may choose to do some or all of their modeling in Verilog performance reasons (using real variables, etc.). Having this system task available in initial blocks would allow these users to do this.

    http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=381

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