enhancement/386: ANALYZED - user defined functions on instantiations

From: etf@boyd.com
Date: Wed Aug 06 2003 - 07:15:39 PDT

  • Next message: Shalom Bresticker: "Re: enhancement/386: ANALYZED - user defined functions on instantiations"

    Precedence: bulk

    First, a correction to the proposal. What the AMS folks are actually calling for here is the ability to call user defined *HDL* functions in parameter overrides. For example, assume we have a Verilog function as follows:

    function real f_mod(a, b)
    input a; real a;
    input b; real b;
    begin
            f_mod = (a-b*((a+0.5)/b)) ;
    end
    endfunction

    Then what we want to be able to do is use this function to set the value of a parameter as follows:

       parameter real aa= 10.0;
       parameter real bb=3.0;
       my_mod #(.r(a*f_mod(aa,bb)+b)) r1 (n1,n2);

    The need for this arises from the need to specify more complex parameter expressions in analog netlists as represented in Verilog-AMS or Verilog.

    It should be noted that this is very similar to what is currently allowed in VHDL-AMS in setting values of generics. This may or may not be a good reason to support it in Verilog as well.

    http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=386

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