From: Scott Cranston (cranston@cadence.com)
Date: Wed Aug 06 2003 - 07:50:02 PDT
Precedence: bulk
The following reply was made to PR enhancement/386; it has been noted by GNATS.
From: "Scott Cranston" <cranston@cadence.com>
To: <etf-bugs@boyd.com>
Cc:
Subject: RE: enhancement/386: ANALYZED - user defined functions on instantiations
Date: Wed, 6 Aug 2003 10:48:21 -0400
Only constant *expressions*. Function calls are not assumed to be
non-constant. I suppose we need a definition of a constant function
here, and then add this restriction to the original proposal.
From the LRM section on defparams:
------
The expression on the right-hand side of the defparam assignments shall
be a constant expression involving
only numbers and references to parameters.
------
There is no similar restriction mentioned in the instantion override
sections, but one would assume it is implied.
+++-----Original Message-----
+++From: Shalom Bresticker [mailto:Shalom.Bresticker@motorola.com]
+++Sent: Wednesday, August 06, 2003 10:30 AM
+++To: etf-bugs@boyd.com
+++Subject: Re: enhancement/386: ANALYZED - user defined
+++functions on instantiations
+++
+++
+++Precedence: bulk
+++
+++The following reply was made to PR enhancement/386; it has
+++been noted by GNATS.
+++
+++From: Shalom Bresticker <Shalom.Bresticker@motorola.com>
+++To: etf-bugs@boyd.com
+++Cc:
+++Subject: Re: enhancement/386: ANALYZED - user defined
+++functions on instantiations
+++Date: Wed, 06 Aug 2003 17:19:44 +0300
+++
+++ Don't we already allow use of constant functions in
+++parameter overrides?
+++
+++ Shalom
+++
+++
+++ etf@boyd.com wrote:
+++
+++ > Precedence: bulk
+++ >
+++ > First, a correction to the proposal. What the AMS folks
+++are actually calling for here is the ability to call user
+++defined *HDL* functions in parameter overrides. For example,
+++assume we have a Verilog function as follows: > > function
+++real f_mod(a, b) > input a; real a; > input b; real b; > begin
+++ > f_mod = (a-b*((a+0.5)/b)) ;
+++ > end
+++ > endfunction
+++ >
+++ > Then what we want to be able to do is use this function
+++to set the value of a parameter as follows: >
+++ > parameter real aa= 10.0;
+++ > parameter real bb=3.0;
+++ > my_mod #(.r(a*f_mod(aa,bb)+b)) r1 (n1,n2);
+++ >
+++ > The need for this arises from the need to specify more
+++complex parameter expressions in analog netlists as
+++represented in Verilog-AMS or Verilog. > > It should be
+++noted that this is very similar to what is currently allowed
+++in VHDL-AMS in setting values of generics. This may or may
+++not be a good reason to support it in Verilog as well. > >
http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=386
--
Shalom Bresticker
Shalom.Bresticker@motorola.com
Design & Reuse Methodology Tel: +972 9
9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9
9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50
441478
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