errata/225: PROPOSAL - The fourth port direction

From: asic@sympatico.ca
Date: Sun Aug 10 2003 - 17:07:01 PDT

  • Next message: Shalom Bresticker: "Re: errata/225: PROPOSAL - The fourth port direction"

    Precedence: bulk

    Add the example:

    module m (.p({a,b})) ;
               input a;
               output b;
               not(b,a);
               endmodule

    at the end of the examples section in 12.3.3.
    Add a comment that mixed IO is allowed in an expression that is a concatenation.
    Stu Sutherland tried it in Verilog-XL, NC, VCS and ModelSim and it is legal.

    Regards,

           Anders

    http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=225

    This archive was generated by hypermail 2.1.4 : Sun Aug 10 2003 - 17:07:55 PDT and
    sponsored by Boyd Technology, Inc.