Re: errata/225: PROPOSAL - The fourth port direction

From: David Roberts (roberts@cadence.com)
Date: Mon Aug 11 2003 - 10:30:01 PDT

  • Next message: Dennis Marsa: "Re: errata/225: PROPOSAL - The fourth port direction"

    Precedence: bulk

    The following reply was made to PR errata/225; it has been noted by GNATS.

    From: David Roberts <roberts@cadence.com>
    To: Charles Dawson <chas@cadence.com>
    Cc: Shalom Bresticker <Shalom.Bresticker@motorola.com>, ptf@boyd.com,
       etf-bugs@boyd.com
    Subject: Re: errata/225: PROPOSAL - The fourth port direction
    Date: Mon, 11 Aug 2003 13:25:30 -0400

     Charles Dawson writes:
    > Precedence: bulk
    >
    > I've been trying to think of why we needed this, and I think I have come
    > up with something. In VPI, for any given port handle you can ask what it's
    > direction would be. In the case of a concatenation, there would be no answer
    > without vpiMixedIO. If it got vpiMixedIO, a reasonable application would
    > then iterate on the bits of the port and fetch the direction for each bit.
    > This is not something that is very relevant from the HDL perspective.
     
     Nope.
     
     It's needed becuase of a definition like
     
       module why(.y());
     
     
     Port "y" has no direction.
     
        --David Roberts
     
    >
    > -Chas
    >
    >
    > Shalom Bresticker wrote:
    > > Precedence: bulk
    > >
    > > Question:
    > >
    > > In Annex G (vpi_user.h), on p. 818 of 1364-2001b, the following appears:
    > >
    > > #define vpiDirection 20 /* direction of port: */
    > > #define vpiInput 1 /* input */
    > > #define vpiOutput 2 /* output */
    > > #define vpiInout 3 /* inout */
    > > #define vpiMixedIO 4 /* mixed input-output */
    > > #define vpiNoDirection 5 /* no direction */
    > >
    > > What does "no direction" mean?
    > >
    > > Thanks,
    > > Shalom
    > >
    > >
    > > asic@sympatico.ca wrote:
    > >
    > >
    > >>Add the example:
    > >>
    > >>module m (.p({a,b})) ;
    > >> input a;
    > >> output b;
    > >> not(b,a);
    > >> endmodule
    > >>
    > >>at the end of the examples section in 12.3.3.
    > >>Add a comment that mixed IO is allowed in an expression that is a concatenation.
    > >>Stu Sutherland tried it in Verilog-XL, NC, VCS and ModelSim and it is legal.
    > >>
    > >>Regards,
    > >>
    > >> Anders
    > >>
    > >>http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=225
    > >
    > >
    > > --
    > > Shalom Bresticker Shalom.Bresticker@motorola.com
    > > Design & Reuse Methodology Tel: +972 9 9522268
    > > Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
    > > POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
    > >
    > >
    > >
    > >
    >
    >
    > --
    > Charles Dawson
    > Senior Engineering Manager
    > NC-Verilog Team
    > Cadence Design Systems, Inc.
    > 270 Billerica Road
    > Chelmsford, MA 01824
    > (978) 262 - 6273
    > chas@cadence.com
    >
    >
    >

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