enhancement/436: Non-blocking event trigger

From: lawrence@cadence.com
Date: Fri Aug 22 2003 - 15:31:21 PDT

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    >Number: 436
    >Category: enhancement
    >Originator: Jay Lawrence - Cadence Design Systems
    >Environment:

    >Description:

    The triggering of named events in Verilog can often lead to race conditions. The following example shows the problem.

        module events;

            event e, go;

            always @(go)
            begin
                    $display($time,,"Always 1 - triggering e");
                    -> e;
            end

            always @(go)
            begin
                    $display($time,,"Always 2 - about to wait on e");
                    @(e) $display($time,,"Always 2 - wakeup on e");
                    $finish;
            end

            always #5 ->go;

         endmodule

    The runtime output of this description could either be:

                       5 Always 1 - triggering e
                       5 Always 2 - about to wait on e
                      10 Always 1 - triggering e
                      10 Always 2 - wakeup on e
    or

                       5 Always 2 - about to wait on e
                       5 Always 1 - triggering e
                       5 Always 2 - wakeup on e

    Note: The output above was generated by running Verilog-XL on the above module with the order of the declaration of the always blocks once as shown, and then with them reversed!

    This ambiguity is created because event triggers act like blocking assignments. They immediately trigger the event at the point at which the trigger is executed. The solution to this problem is to allow a non-blocking trigger operator.

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