enhancement/442: Add auto-increment and auto-decrement statements

From: lawrence@cadence.com
Date: Mon Aug 25 2003 - 05:06:06 PDT

  • Next message: lawrence@cadence.com: "enhancement/442: PROPOSAL - Add auto-increment and auto-decrement statements"

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    >Number: 442
    >Category: enhancement
    >Originator: Jay Lawrence - Cadence Design Systems
    >Environment:

    >Description:

    This enhancment request proposes the addition of the increment assignment and decrement assignment statements in Verilog.

    An extremely common operation in Verilog is incrementing or decrementing by 1. The following proposal allows ++ and -- as a shortcut for this operation as a statement in the language. This is done by providing an alternative syntax for the blocking_assignment.

    Note that this proposal does not allow the use of ++ or -- in expressions. The addition of these as expressions adds undue ambiguity to the language as demonstrated by the following example.

            reg [2:0]

            i = 0;
            r[i] = i++;

    Depending on the ordering of evaluation of the bit select i (A), the right-hand side i (B), and the increment operator (C), the following results are possible.

            r[0] = 0; // A, B, C or B, A, C
            r[1] = 0; // B, C, A

    The combinations A, C, B and C, A, B and C, B, A are not possible if you treat ++ as a post-increment operator as in 'C'.

    'C' does allow this use and the ambiguity. The ambiguity is alleviated somewhat by the introduction of "sequence points" in the ANSI-C standard however it is not eliminated. Given the common usage in Verilog (for loop headers and while loop bodies), the additional syntax required is not worth the ambiguity.

            i = 0;
            while (i < 32) {
                    r[i] = i;
                    i++;
            }

    vs

            while (i < 32) {
                    r[i] = i++;
            }

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