RE: enhancement/442: Add auto-increment and auto-decrement statements

From: Jay Lawrence (lawrence@cadence.com)
Date: Tue Aug 26 2003 - 17:20:00 PDT

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    The following reply was made to PR enhancement/442; it has been noted by GNATS.

    From: "Jay Lawrence" <lawrence@cadence.com>
    To: "Stephen Williams" <steve@icarus.com>, <etf-bugs@boyd.com>
    Cc:
    Subject: RE: enhancement/442: Add auto-increment and auto-decrement statements
    Date: Tue, 26 Aug 2003 20:14:41 -0400

     Thanks for the comment/suggestions Steve. I considered all the +=, -=,
     ... Variations and in my own opinion decided they just weren't common
     enough to bother with. Especially when you consider that non-blocking
     versions of all of them really should be included.
     
     In the typical case of anything but +/- constant I end up writing
     
             i += (x + y);
     
     I include the () out of pure paranoia and to make it easier to read.
     
     Instead of:
     
             i = i + x + y;
     
     There is a one character difference.
     
     FYI, SystemVerilog does include all of these, but without non-blocking
     variations.
     
     
     Jay
     
     ===================================
     Jay Lawrence
     Senior Architect
     Functional Verification
     Cadence Design Systems, Inc.
     (978) 262-6294
     lawrence@cadence.com
     ===================================
     
    > -----Original Message-----
    > From: Stephen Williams [mailto:steve@icarus.com]
    > Sent: Tuesday, August 26, 2003 7:48 PM
    > To: etf-bugs@boyd.com
    > Cc: Jay Lawrence
    > Subject: Re: enhancement/442: Add auto-increment and
    > auto-decrement statements
    >
    >
    > lawrence@cadence.com wrote:
    > > Precedence: bulk
    > >
    > >
    > >
    > >>Number: 442
    > >>Category: enhancement
    > >>Originator: Jay Lawrence - Cadence Design Systems
    > >>Environment:
    > >
    > >
    > >>Description:
    > >
    > >
    > >
    > > This enhancment request proposes the addition of the
    > increment assignment
    > > and decrement assignment statements in Verilog.
    > >
    > > An extremely common operation in Verilog is incrementing or
    > decrementing
    > > by 1. The following proposal allows ++ and -- as a
    > shortcut for this
    > > operation as a statement in the language. This is done by
    > providing an
    > > alternative syntax for the blocking_assignment.
    > >
    > > Note that this proposal does not allow the use of ++ or --
    > in expressions.
    > > > The addition of these as expressions adds undue ambiguity to the
    > language
    > > as demonstrated by the following example.
    > >
    > > reg [2:0]
    > >
    > > i = 0;
    > > r[i] = i++;
    >
    > Rather then the ++ and -- operators, which have subtle and
    > undesireable connotations, perhaps instead define compressed
    > assignment operators:
    >
    > i = 0;
    > while (i < 32) {
    > r[i] = i;
    > i += 1;
    > }
    >
    > The advantage here, too, is that it is far more general. You
    > can increment/decrement by other values, even non-constant values,
    > and it is fairly easy to define other similar opeators a la "C":
    >
    > +=, -=, &=, |= ^=, *=, /=, >>=, <<=, etc.
    >
    > These are in fact read-modify-write statements, so should be
    > restricted to precedural code. Syntactically, these would be
    > the same as <=, so these would be easy to add to the BNF and
    > *far* easier to explain then restricted ++ and -- operators.
    >
    > Open question: Non-blocking variants?
    > --
    > Steve Williams "The woods are lovely, dark and deep.
    > steve at icarus.com But I have promises to keep,
    > http://www.icarus.com and lines to code before I sleep,
    > http://www.picturel.com And lines to code before I sleep."
    >
    >

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