Re: enhancement/442: Add auto-increment and auto-decrement statements

From: Stephen Williams (steve@icarus.com)
Date: Tue Aug 26 2003 - 18:00:01 PDT

  • Next message: Jay Lawrence: "RE: enhancement/442: Add auto-increment and auto-decrement statements"

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    The following reply was made to PR enhancement/442; it has been noted by GNATS.

    From: Stephen Williams <steve@icarus.com>
    To: Jay Lawrence <lawrence@cadence.com>
    Cc: etf-bugs@boyd.com
    Subject: Re: enhancement/442: Add auto-increment and auto-decrement statements
    Date: Tue, 26 Aug 2003 17:53:05 -0700

     Jay Lawrence wrote:
     
    > Thanks for the comment/suggestions Steve. I considered all the +=, -=,
    > ... Variations and in my own opinion decided they just weren't common
    > enough to bother with. Especially when you consider that non-blocking
    > versions of all of them really should be included.
    >
    > In the typical case of anything but +/- constant I end up writing
    >
    > i += (x + y);
    >
    > I include the () out of pure paranoia and to make it easier to read.
    >
    > Instead of:
    >
    > i = i + x + y;
    >
    > There is a one character difference.
     
     So write "i = i + x + y;" if you would rather. The point is that
     the degenerate case of "i += 1;" has most all the advantages of
     your "i ++;" example without the limitations or ickyness. You are
     rubbing a C programmer's fur the wrong way when you define a ++
     statement (you've defined a statement, not an operator) is that
     it looks exactly like a "C" thing, and sorta goes half way.
     
     Here's another advantage:
     
           i += #5ns 1;
     
     Looks familiar? Or this more tricky example:
     
           for (i = 0 ; i < 32 ; i <<= #5 1) begin
                /* stuff */
           end
     
     OK, maybe that's a bit too slick, but my point is that the compressed
     assignment statements are more naturally Verilog so the consequences
     are obvious, BNF changes to support it would be very minimal.
     
     I think you can see pretty clearly how these can be implemented
     easily in simulators and synthesizers.
     
    > FYI, SystemVerilog does include all of these, but without non-blocking
    > variations.
     
     SystemVerilog also includes ++/--, side effects and all. Do you
     really want that? SystemVerilog also defines the compressed
     assignments as *operators* with side effects, a very very bad
     idea, I think. I propose they be assignments, and *not* operators.
     
     --
     Steve Williams "The woods are lovely, dark and deep.
     steve at icarus.com But I have promises to keep,
     http://www.icarus.com and lines to code before I sleep,
     http://www.picturel.com And lines to code before I sleep."
     

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