Date: Sat Aug 30 2003 - 14:32:49 PDT
A proposal on extending Verilog to add the verification
layer that contains commands and constructs to be used
for writting test benchs for verification of hardware
It includes object-oriented programming support for
writing modular and reusable test benches, procedural code
execution with dynamic concurrent programming support,
various synchronization/mutex primitives for multi-threaded
execution, cycle based test bench construction support,
enhanced list and array data types for high level behavior
modeling, and aspect-oriented programming support.
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