Re: errata/332: 12.3.3 -- port direction declarations that don't mention the size of port

From: Shalom.Bresticker@motorola.com
Date: Wed Sep 03 2003 - 06:50:01 PDT

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    The following reply was made to PR errata/332; it has been noted by GNATS.

    From: Shalom.Bresticker@motorola.com
    To: etf-bugs@boyd.com
    Cc: Yair Lipa <yairl@msil.sps.mot.com>
    Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't
     mention the size of port
    Date: Wed, 3 Sep 2003 16:42:41 +0300 (IDT)

     Reminder: the case was
     
     module m(in);
     input in ;
     wire [7:0] in ;
     endmodule
     
     Most of us seem to have agreed that it is to be considered illegal.
     Today I found that not only Verilog-XL accepts it, but so does VCS and NCV.
     All three tools also agree to consider the port as 8 bits, not as a scalar.
     
     Should we change the standard to be compatible with the tools,
     or remain strict ?
     
     Shalom
     
     
     On Wed, 16 Apr 2003, Steven Sharp wrote:
     
    > Date: Wed, 16 Apr 2003 10:40:03 -0700
    > From: Steven Sharp <sharp@cadence.com>
    > To: etf-bugs@boyd.com
    > Subject: Re: errata/332: 12.3.3 -- port direction declarations that don't
         mention the size of port
    >
    > >There are no examples like this in the LRM, and it seems OK to me,
    > >but it almost runs afoul of this sentence in 12.3.3 --
    > >
    > > "If the net or variable is declared as a vector, the range
    > > specification between the two declarations of a port shall
    > > be identical."
    > >
    > >I don't know what is meant by 'between' here, but in the code example,
    > >only the reg or wire declarations include a range specification, so
    > >there's nothing to be identical with.
    >
    > Which means it isn't identical. No range specification (which means
    > a scalar) is clearly not an identical range specification to any
    > actual range specification.
    >
    > In practice, Verilog-XL did not do strict checking. It will catch
    > a port declared as a vector and then declared as a scalar, but not
    > vice-versa. It will not catch mismatching ranges (apparently using
    > the one from the reg/wire, not the port). The only time the range
    > from the port seems to matter in XL is if there is no declaration for
    > the reg/wire. Other tools have probably followed suit.
     
     --
     Shalom Bresticker Shalom.Bresticker@motorola.com
     Design & Reuse Methodology Tel: +972 9 9522268
     Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
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