From: David Roberts (firstname.lastname@example.org)
Date: Thu Sep 04 2003 - 07:00:01 PDT
The following reply was made to PR errata/237; it has been noted by GNATS.
From: David Roberts <email@example.com>
Cc: David Roberts <firstname.lastname@example.org>, email@example.com
Subject: Re: errata/237: PROPOSAL - A.7.5.3: scalar_timing_check_expressions
Date: Thu, 4 Sep 2003 09:53:11 -0400
> That still leaves the issue of whether the timing check should be
> enabled or not when the condition is X or Z.
The only comment I can make is that, what is presently in the IEEE
1364-2001 standard ignoring the confusing gobbledygook wording.
"When comparisons are deterministic, an X value on the conditioning
signal shall not enable the timing check. For nondeterministic
comparisons, an X on the conditioning signal shall enable the
This was the origional documented to behavior of Verilog-XL. It
is the way Verilog-XL presently behaves. NCV has also implimented
the same behavior. Changing this behavior would have a nasty impact
Changing the behavior would make the behavior of simulators supporting
the different version of the IEEE-1364 incompatible. I do not see
this part of the issue as an errata.
Cadence Design Systems, Inc.
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