Re: errata/237: PROPOSAL - A.7.5.3: scalar_timing_check_expressions has redundancies

From: David Roberts (roberts@cadence.com)
Date: Thu Sep 04 2003 - 07:00:01 PDT

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    The following reply was made to PR errata/237; it has been noted by GNATS.

    From: David Roberts <roberts@cadence.com>
    To: Shalom.Bresticker@motorola.com
    Cc: David Roberts <roberts@cadence.com>, etf-bugs@boyd.com
    Subject: Re: errata/237: PROPOSAL - A.7.5.3: scalar_timing_check_expressions
     has redundancies
    Date: Thu, 4 Sep 2003 09:53:11 -0400

     Shalom.Bresticker@motorola.com writes:
    > Thanks.
    >
    > That still leaves the issue of whether the timing check should be
    > enabled or not when the condition is X or Z.
     
     The only comment I can make is that, what is presently in the IEEE
     1364-2001 standard ignoring the confusing gobbledygook wording.
     
       "When comparisons are deterministic, an X value on the conditioning
        signal shall not enable the timing check. For nondeterministic
        comparisons, an X on the conditioning signal shall enable the
        timing check."
     
     This was the origional documented to behavior of Verilog-XL. It
     is the way Verilog-XL presently behaves. NCV has also implimented
     the same behavior. Changing this behavior would have a nasty impact
     on users.
     
     Changing the behavior would make the behavior of simulators supporting
     the different version of the IEEE-1364 incompatible. I do not see
     this part of the issue as an errata.
     
     
         --David Roberts
           Cadence Design Systems, Inc.
     
    >
    > --
    > Shalom Bresticker Shalom.Bresticker@motorola.com
    > Design & Reuse Methodology Tel: +972 9 9522268
    > Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
    > POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
    >
    >



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