errata/463: 4.1.13: Zero fill in ?: even if signed or x/z

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Sep 04 2003 - 14:10:25 PDT

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    >Number: 463
    >Category: errata
    >Originator: "Brad Pierce" <Brad.Pierce@synopsys.com>
    >Environment:
    >Description:

    Section 4.1.13 says, regarding

         ( expression1 ? expression2 : expression3 )

    that "If the lengths of expression2 and expression3 are different,
    the shorter operand shall be lengthened to match the longer and
    zero-filled from the left (the high-order end)."

    First, "(the high-order end)" should be deleted.

    More importantly, this behavior seems inconsistent with the rest
    of Verilog. The following example --

    module m (output reg signed [31:0] o1, o2);
      initial begin
         o1 = ( 1'b0 ? 10'sb0000000000 : 10'sb1111111110 ) ;
         $displayb(o1);
         o2 = ( 1'b0 ? 10'sb0000000000 : 9'sb111111110 ) ;
         $displayb(o2);
      end
    endmodule

    yields

       11111111111111111111111111111110
       00000000000000000000000111111110

    Was this really the intent?

    -- Brad

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