From: Clifford E. Cummings (email@example.com)
Date: Thu Sep 11 2003 - 14:49:20 PDT
Hi, Shalom -
At 05:57 PM 9/11/03 +0300, Shalom Bresticker wrote:
>Where are the UDP scheduling semantics described, especially for sequential
UDP scheduling semantics are not described and they have been implemented
differently by different vendors. In my opinion, combinational UDPs should
be scheduled into the Active Events Queue and sequential UDPs (any UDP that
has a reg declaration) should be scheduled the same as nonblocking
assignments; that is, the inputs should be evaluated in the Active Events
Queue and the output should be scheduled into the Nonblocking Update Events
Queue. This is the how we can guarantee that a pipeline of UDP flip-flops
simulates like the RTL and like real hardware.
I think the last time I checked, VCS and Verilog-XL simulated as described
above and ModelSim and NC-Verilog had races (did all scheduling in the
Active Events Queue), but it has been a while since I ran this test.
Regards - Cliff
>I thought I had seen them once, but I cannot find them,
>and I am no longer sure they are really described.
>Shalom Bresticker Shalom.Bresticker@motorola.com
>Design & Reuse Methodology Tel: +972 9 9522268
>Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
>POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
firstname.lastname@example.org / www.sunburst-design.com
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