From: Stephen Williams (firstname.lastname@example.org)
Date: Fri Sep 12 2003 - 16:35:00 PDT
>Originator: Stephen Williams <email@example.com>
This issue has been getting under my skin recently, as I find
that there is a significant difference of opinion how the UDP
output is supposed to be scheduled when the UDP is synchronous.
I'm trying to decide what is right in my own implementation.
I have heard now that NC-Verilog and VCS both schedule synchronous
udp outputs as non-blocking assignments, but that ModelSim schedules
them like blocking assignments. I've heard reasoned arguments on
both sides of this, so it is abundently clear to me that this is
under-specified by the standard. (Reasonable people case to
I propose that the *synchronous* output of user defined primitives
be scheduled as non-blocking assignments. This matches the behavior
of the assignment most commonly used to infer synchronous (RTL)
logic in the first place, so would lead to more consistent behavior.
I suggest that the *combinational* output of user defined primitives
are scheduled as normal gate propagation events. Makes sense, and
matches commonly expected behavior.
-- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
This archive was generated by hypermail 2.1.4
: Sun Sep 14 2003 - 17:23:14 PDT
sponsored by Boyd Technology, Inc.