errata/441: PROPOSAL - 3.2.2, 4.1.6: Nets also have signedness

From: Brad.Pierce@synopsys.com
Date: Sun Sep 14 2003 - 21:14:51 PDT

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    In the CAUTION box of 3.2.2

    CHANGE

       "Variables can be assigned negative values,
        but only signed regs, integer, real, and
        realtime variables shall retain the significance
        of the sign. The unsigned reg and time variables
        shall treat the value assigned to them as an
        unsigned value. Refer to 4.1.6 for a description
        of how signed and unsigned variables are treated
        by certain Verilog operators."

    TO

       "Nets and variables can be assigned negative values,
        but only integer, real, realtime and signed reg
        variables and signed nets shall retain the
        significance of the sign. Time and unsigned
        reg variables and unsigned nets shall treat the
        value assigned to them as an unsigned value.
        Refer to 4.1.6 for a description of how signed
        and unsigned nets and variables are treated by
        certain Verilog operators."

    and in 4.1.6

    CHANGE

       "A reg data type shall be treated as an unsigned
        value unless explicitly declared to be signed.
        An integer variable shall be treated as signed.
        Signed values shall use a 2's complement
        representation."

    TO

       "A value assigned to a reg variable or net
        shall be treated as an unsigned value unless
        the reg variable or net has been explicitly
        declared to be signed. A value assigned to an
        integer, real or realtime variable shall be treated
        as signed. A value assigned to a time variable
        shall be treated as unsigned. Signed values,
        except for those assigned to real and realtime
        variables, shall use a 2's complement representation.
        Values assigned to real and realtime variables
        shall use a floating-point representation."

    http://boydtechinc.com/cgi-bin/issueproposal.pl?cmd=view&pr=441

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