From: Stephen Williams (email@example.com)
Date: Mon Sep 15 2003 - 18:57:51 PDT
Steven Sharp wrote:
> They may be seeing a UDP output change that is delayed until after
> some other events, and assuming that it must be on the NBA queue.
> But it is hard to tell whether the change happened just before the
> NBA queue, or at the beginning of the NBA queue.
OK, by your reasoning, the attached sample has a race in it.
To wit, the "ce" which is registered by a sequential primitive
may get to another thread or device that is activated by the
same clock but uses the "ce" as an enable.
In Icarus Verilog, it turns out that all the clocked devices
are activated at once, and subsequent events are enqueued in
FIFO order within an activation queue, so in my simulator there
is no race for this example.
But a simulator that processes all propagation events, including
the output of the sequential primitive, before it processes any
activated behavioral threads, might turn on the "ce" before the
thread that reads it is scheduled. The "out" value would then
activate one clock too early. The same device, modeled with a
non-blocking assignment, is free of races.
I can contrive slightly more complicated examples that have
races (assuming "active" scheduling) even with purely FIFO
schedulers, but the ideas in my head put combinational logic
on one clock input.
These are exactly the sorts of complaints I hear from users,
and why I've heard of some writing udps out of their libraries.
-- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
primitive FF(Q, C, D);
input D, C;
initial Q = 0;
// C D Q Q+
(01) 0 : ? : 0 ;
(01) 1 : ? : 1 ;
(0?) 1 : 1 : 1 ;
(0?) 0 : 0 : 0 ;
(?0) ? : ? : - ;
? (??) : ? : - ;
endprimitive // FF
#5 clk = 0;
#5 clk = 1;
reg [1:0] count = 0;
always @(posedge clk) count <= count + 1;
// ce is a delayed count. It is common to use a delayed
// enable to match pipeline delays.
FF delay_by_1 (ce, clk, count);
// This is a trivial thread that uses the delayed ce. The
// out value should take a 1 value on the clk *after* the
// ce goes active, and fall on the clk after ce goes inactive.
// This is normal synchronous logic pipelining.
reg out = 0;
always @(posedge clk)
out <= 1'b1;
out <= 1'bz;
// If the ce update is scheduled before the "out" thread is
// executed (FIFO order is not guaranteed) then the out value
// will change one clk too soon.
$monitor("clk=%b, count=%b, ce=%b, out=%b", clk, count, ce, out);
endmodule // top
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