RE: errata/467: assignments on port declarations 12.3

From: Michael McNamara (mac@verisity.com)
Date: Fri Sep 19 2003 - 16:50:01 PDT

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    The following reply was made to PR errata/467; it has been noted by GNATS.

    From: Michael McNamara <mac@verisity.com>
    To: sharp@cadence.com
    Cc: etf-bugs@boyd.com
    Subject: RE: errata/467: assignments on port declarations 12.3
    Date: Fri, 12 Sep 2003 15:54:46 -0700

     I can't cliam there was a real decision to handle it this way; but I
     can confirm that the BNF correctly implements what I recall we
     proposed and talked about. There was no desire to enable the
     specification of a constant driver for an output wire in a design.
     
     Note that the result is the same, at least viewed externally; either
     module if instantiated would have a thing called w that supplies a one
     to whom ever cares to look at it.
     
     Through the PLI one could determine that m.r was a reg, and m.w was a
     wire, but otherwise all would be the same.
     
              module m (output wire w = 0);
     
              module m (output reg r = 0);
     
     -- On Sep 12 2003 at 14:01, sharp@cadence.com sent a message:
    > To: etf-bugs@boyd.com
    > Subject: "errata/467: assignments on port declarations 12.3"
    > Precedence: bulk
    >
    >
    > >Number: 467
    > >Category: errata
    > >Originator: sharp@cadence.com
    > >Environment:
    >
    > >Description:
    >
    > This is a question, probably not a real erratum.
    >
    > Looking at the BNF, it appears to allow reg declaration
    > initializers on reg port declarations, both the combined
    > reg port declarations inside the module and the ANSI-C
    > style reg port declarations in the port list.
    >
    > It does not allow continuous assignments on net declarations
    > if those are net port declarations, whether those are
    > combined net port declarations inside the module or ANSI-C
    > style net port declarations in the port list.
    >
    > So the BNF allows both
    >
    > module m (output reg r = 0);
    >
    > and
    >
    > module m (r);
    > output reg r = 0;
    >
    > But it does not allow either
    >
    > module m (output wire w = 0);
    >
    > or
    >
    > module m (w);
    > output wire w = 0;
    >
    > even though it allows
    >
    > module m (w);
    > output w;
    > wire w = 0;
    >
    > Is this what was intended? I can see some logic to this,
    > since you can't really assign much besides constants this
    > way (at least in the ANSI-C style port declarations).
    > That makes sense for a reg initializer, but is of limited
    > use for a continuous assignment.
    >
    > I checked the email archives, but couldn't find anything
    > related to this.

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