Re: errata/484: 10.3.4.e: assignment of function result value

From: Steven Sharp (sharp@cadence.com)
Date: Mon Sep 22 2003 - 12:30:00 PDT

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    The following reply was made to PR errata/484; it has been noted by GNATS.

    From: Steven Sharp <sharp@cadence.com>
    To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com
    Cc:
    Subject: Re: errata/484: 10.3.4.e: assignment of function result value
    Date: Mon, 22 Sep 2003 16:13:02 -0400 (EDT)

     It is a pretty weak requirement. I suppose it might save you from some gross
     errors. Verilog-XL doesn't bother to do any checks of this sort.
     
     To answer your other question, there is nothing that says it is illegal to
     fall off the end of the function without assigning to the return variable.
     There is no requirement for a simulator to issue an error when this happens.
     One reason why not is that it would cost speed in the simulator to do this
     kind of run-time checking.
     
     Steven Sharp
     sharp@cadence.com
     

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