errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2)

From: sharp@cadence.com
Date: Tue Sep 23 2003 - 16:57:17 PDT

  • Next message: Brad Pierce: "Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2)"

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    >Number: 487
    >Category: errata
    >Originator: sharp@cadence.com
    >Environment:

    >Description:

    The rules in 3.11.1 and 12.2 specify more or less that when
    a parameter has an explicit type, the value assigned to it
    by whatever means will be converted to that type. However,
    the meaning of this is not clear. It could be evaluated as
    a self-determined expression, and then the value converted
    to the type of the parameter. But this is not consistent
    with all other situations in Verilog. These are effectively
    assignments, and the evaluation of the value should be done
    in the context of the left hand side, i.e. the type of the
    parameter. I have been assuming that this was obvious, but
    it may not be. Here is a simple example:

    parameter [31:0] ip = 4'b1101 << 15;

    If the value is evaluated as self-determined, the width will
    be 4, and the value will overflow to 4'b0, and then be
    converted at the end to 0. If it is evaluated in context,
    the width will be 32, and the value will not overflow.
    It will be 32'b1101000000000000000, which is presumably
    what was desired.

    The same should apply to a parameter override with an
    expression.

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