Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2)

From: Steven Sharp (sharp@cadence.com)
Date: Wed Sep 24 2003 - 14:10:00 PDT

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    The following reply was made to PR errata/487; it has been noted by GNATS.

    From: Steven Sharp <sharp@cadence.com>
    To: etf-bugs@boyd.com, Brad.Pierce@synopsys.com
    Cc:
    Subject: Re: errata/487: Unclear parameter type conversion rules (3.11.1 and 12.2)
    Date: Wed, 24 Sep 2003 17:57:06 -0400 (EDT)

    > Parameter types are polymorphic and dependent on
    > the type of the value assigned to the parameter?
     
     If the parameter has no explicit type declared, then yes. This was always
     the case in Verilog-1995, since parameters could not have an explicit type
     declared in Verilog-1995.
     
     In Verilog-2001, it is legal to declare a type (integer, real, signed or
     unsigned vector with range) on a parameter declaration. In that case, its
     type is set by the declaration, rather than the value assigned.
     
     The cited sections (3.11.1 and 12.2) give detailed rules for determining
     the type of a parameter in all situations.
     
    > So, for example, if P is declared
    >
    > parameter [31:0] P = 4'b0000
    >
    > it is really only 4 bits wide, not 32, and if it
    > is overridden with 5'b00001, it is 5 bits wide?
     
     Since you declared P with an explicit range [31:0], then no. But if you
     left the range off, then yes. It would change width when it changed value.
     
     That part is all clear.
     
     This erratum is about the details of value conversion when there is an
     explicit type declared and it is not the same as the value.
     
     Steven Sharp
     sharp@cadence.com
     

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