Re: errata/483: 4.2: Bit/part-selects of parameters

From: Steven Sharp (sharp@cadence.com)
Date: Fri Sep 26 2003 - 09:50:01 PDT

  • Next message: Steven Sharp: "Re: errata/486: 12.3.3: Implicit nets are not necessarily unsigned"

    Precedence: bulk

    The following reply was made to PR errata/483; it has been noted by GNATS.

    From: Steven Sharp <sharp@cadence.com>
    To: sharp@cadence.com, Shalom.Bresticker@motorola.com
    Cc: etf-bugs@boyd.com
    Subject: Re: errata/483: 4.2: Bit/part-selects of parameters
    Date: Fri, 26 Sep 2003 13:33:21 -0400 (EDT)

     Yes, you are correct that the LRM uses the term "data type" to refer to
     the distinction between variables and nets (and then in 3.11, parameters
     are stated to be distinct from either). It fails to properly distinguish
     between how objects "are assigned and hold values" (3.2), and what is
     traditionally called a data type in any other language, which is the set of
     values an object can hold. The closest it gets to this is the "value set"
     described in 3.1, which completely leaves out the fact that there is an
     alternative value set called reals. The proposed Extended Data Types
     enhancement distinguishes these two aspects of an object, and makes them
     orthogonal (something that already started with parameters being declared
     as integer, real, realtime, time or a vector of the "Verilog HDL value set"
     from 3.1).
     
     I will try to use the current LRM terminology in the rest of this. A
     parameter is never of the reg data type. A reg is one of the variable
     data types (3.2 and 3.2.2). A parameter does not belong to either the
     variable or net group (see 3.11). Therefore a parameter is inherently
     never of a reg data type. It can hold the same "Verilog HDL value set"
     as a reg, but that does not make it a reg. As stated in 3.1, "almost all
     of the data types in the Verilog HDL store all four basic values."
     
     The statement in 10.3.1 that a function "defaults to a one bit reg for
     the return value", is more mixed up and sloppy terminology. A function
     is not a reg, it is a function, which is a different class of object.
     This sloppy terminology is probably used because there is no proper
     terminology in the LRM for what would be called a "data type" in another
     language. What is meant is "one bit of the Verilog HDL value set described
     in 3.1", but that is rather clumsy. The confusion here is worsened by the
     fact that there _is_ a variable implicitly declared inside the function, with
     the same name as the function (10.3.2).
     
     At any rate, this same kind of defaulting does not apply to a parameter
     anyway. A parameter with no explicit type does not default to "one bit of
     the Verilog HDL value set described in 3.1". It defaults to the type of
     the expression that it gets set to, which is either a real, or a signed or
     unsigned vector of bits of "the Verilog HDL value set described in 3.1".
     
     Steven Sharp
     sharp@cadence.com
     

    This archive was generated by hypermail 2.1.4 : Fri Sep 26 2003 - 09:52:42 PDT and
    sponsored by Boyd Technology, Inc.