Re: enhancement/404: add wildcards for equality operators

From: Shalom.Bresticker@motorola.com
Date: Mon Sep 29 2003 - 19:00:01 PDT

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    The following reply was made to PR enhancement/404; it has been noted by GNATS.

    From: Shalom.Bresticker@motorola.com
    To: Steven Sharp <sharp@cadence.com>
    Cc: etf-bugs@boyd.com
    Subject: Re: enhancement/404: add wildcards for equality operators
    Date: Tue, 30 Sep 2003 05:43:06 +0300 (IDT)

     When I made my proposal, I was not aware of the SystemVerilog construct.
     I think the Jeda donation also includes a similar construct.
     
    > Apparently SystemVerilog 3.1 added wildcard equality and inequality operators,
    > in section 7.5. The syntax is very similar to my suggestion: =?= and !?=,
    > instead of ==? and !=?. That is probably the syntax I would have suggested
    > for a symmetric compare, but my syntax is more natural for an asymmetric
    > compare (wildcards only in the right operand).
     
     Shalom
     
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     Shalom Bresticker Shalom.Bresticker@motorola.com
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