errata/292: RE: errata/292: 12.3.3 : net declaration before port declaration

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Sat Oct 04 2003 - 20:10:00 PDT

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    The following reply was made to PR errata/292; it has been noted by GNATS.

    From: "Brad Pierce" <Brad.Pierce@synopsys.com>
    To: <etf-bugs@boyd.com>
    Cc:
    Subject: RE: errata/292: 12.3.3 : net declaration before port declaration
    Date: Sat, 4 Oct 2003 11:23:21 -0700

     Contrary to the claim in this thread, I get the following message
     from Verilog-XL 2.7 --
     
     Error! Symbol (x) previously declared [Verilog-SSPRD]
               "file.v", 2:
     1 error
     End of VERILOG-XL 2.7 Oct 4, 2003 11:03:26
     
     for my test case
     
                module m(x);
                wire x;
                input x;
                endmodule
     
     I think it's a natural requirement that any declarations of the
     nets/variables on a port must come after the direction has been
     specified, e.g.,
     
                module m_1(x);
                input wire x;
                endmodule
     or
                module m_2(x);
                input x;
                wire x;
                endmodule
     or
                module m_3(input wire x);
                endmodule
                
     -- Brad
     

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