Date: Wed Nov 19 2003 - 03:22:31 PST
> >All the solutions you have given are synthesizable, but probably give less
> >optimal results.
> Do you mean less optimal than the original nonparameterized version? I
> don't see why this should be impacted for the versions that are multiple
> levels of muxes. They express the exact same functionality as the original.
> It shouldn't matter whether the intermediate mux outputs are explicitly
> declared nets with names, or just unnamed intermediate nodes in a large
> expression tree. They take the same logic to compute.
Theoretically you are correct.
But the fact is that RTL coding style affects implementation.
An if...else if...else if...else if...else gives a different implementation
than a sequence of if statements with equivalent functionality.
This has obvious disadvantages but it also has the advantage that it you can
influence the implementation. Of course the correct way to do it would have
been by // synthesis directives.
> >This is the difference between the way we defined generates and a true text
> Yes, a text preprocessor could produce arbitrary input text to be compiled.
> The problem with a text preprocessor is that it can't be parameterized
> based on Verilog parameter values, since those aren't known until after the
> input is parsed and the design hierarchy is instantiated. That is a severe
> drawback. And note that if you really want a text preprocessor, you could
> always use one to preprocess your source before compiling it, independent
> of anything defined in the Verilog language.
Yes, but the limitations of generates are also severe drawbacks, as my
example shows. And we have additional examples.
As for text preprocessors, the problem is that there is not something
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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