errata/510: : Is "module m(.p(p));" legal?

From: Shalom.Bresticker@motorola.com
Date: Mon Dec 01 2003 - 05:20:00 PST

  • Next message: Stefen Boyd: "errata/227: Re: errata/227: task/function port lists and internal block item declarations"

    >Number: 510
    >Category: errata
    >Originator: Shalom.Bresticker@motorola.com
    >Description:

    This is another port definition question from last year.

    ---------- Forwarded message ----------
    Date: Tue, 13 Aug 2002 16:37:23 +0300
    From: Shalom Bresticker <Shalom.Bresticker@motorola.com>

    1364 allows me to define a module port in the form

    module qq ( .xx(yy) ) ;

    where xx will be the port name,
    and yy is a signal defined within the module.

    In BNF terms, this is

    module qq ( .port_identifier(port_reference) ) ;

    This is called an "explicit port" in 12.3.2.

    My question:

    Is it allowed for port_identifier to use the same name as
    port_reference?

    I.e., module qq ( .yy(yy) ) ;

    I can't find something in 1364-1995 or 2001 which forbids it, but if I
    try to do it in Verilog-XL, I get

    Error! Symbol (yy) previously declared as a port name [Verilog-SPDPD]
              "qq.v", 1:

    I am told that NC-Verilog also rejects it, but VCS accepts it.

    Looks like we need to add a clarification.

    ---------- Forwarded message ----------
    Date: Tue, 13 Aug 2002 21:31:42 -0400
    From: Anders Nordstrom <asic@sympatico.ca>

    Wouldn't the name space rules disallow a declaration like:
    module qq ( .yy(yy) ) ;

    If the port and the signal are in the same scope then you are not allowed to
    have two objects with the same name.

    If it is allowed then, .yy(yy) is the same as yy since the port and the
    signal has the same name and you couldn't distinguish between them so it
    would make sense not to allow it.

    ---------- Forwarded message ----------
    Date: Thu, 15 Aug 2002 09:00:02 +0300 (IDT)
    From: Shalom Bresticker <Shalom.Bresticker@motorola.com>

    I don't see that they are in the same name space.

    The signal "(yy)" is internal to the module, accessible only from within it, or
    by using a hierarchial path name.

    The port ".yy" is the external name of the port, accessible only in a module
    instantiation using port connection by name.

    This archive was generated by hypermail 2.1.4 : Mon Dec 01 2003 - 05:20:02 PST and
    sponsored by Boyd Technology, Inc.