From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Dec 08 2003 - 07:12:36 PST
I suppose that depends on your definition of "at start of simulation".
In Verilog, in general, variables are initialized using the "initial" construct.
This does the same.
Note that there are advantages to having an "always" or a continuous assignment be
activated before the "initial" block.
Suppose you model combinational logic as
always @(a) b = f(a) ;
Then you want b to also be initialized when a is.
If a is initialized before the always block is activated, then the always will not see that
a has changed, and b will therefore not be initialized.
So things are not so simple.
Jayaram Bhasker wrote:
> Mac (thanks to Shalom for his reply as well):
> The semantics as written in the LRM are clear. Maybe it was my assumption or I saw it
> somewhere that the reasoning behind introducing this short-hand notation was to
> provide a feature to initialize a variable at start of simulation. Clearly that
> has not been achieved. Maybe my assumption is wrong . . .
> It would be good to add a note in the standard
> that says that a var decl assignment does not necessarily
> imply that it will have the value at start of simulation.
> - bhasker
> (PS: as a user, I find this confusing. If I say "reg foo = 2", i would expect it to have
> the value 2 at start of simulation).
> J. Bhasker, eSilicon Corp
> 1605 N. Cedar Crest Blvd, Ste 615, Allentown, PA 18104
> firstname.lastname@example.org, 610.439.6831, 610.770.9634(fax)
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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