From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Jan 05 2004 - 08:20:00 PST
>Number: 522
>Category: errata
>Originator: Shalom Bresticker <Shalom.Bresticker@motorola.com>
>Description:
7.14.1 says,
"The syntax for delays on gate primitives (including user-defined primitives;
see Clause 8), nets, and continuous assignments shall allow three values each
for the rising, falling, and turn-off delays. The minimum, typical, and maximum
values for each delay shall be specified as constant expressions separated by
colons. There shall be no required relation (e.g., min <= typ <= max) between
the expressions for minimum, typical, and maximum delays. These can be any three
constant expressions."
In the BNF, these delays are expressed as "delay2" and "delay3".
After the changes of issue 174, they now appear as (see A.2.2.3):
delay3 ::=
# delay_value
| # ( mintypmax_expression [ , mintypmax_expression [ ,
mintypmax_expression ] ] )
delay2 ::=
# delay_value
| # ( mintypmax_expression [ , mintypmax_expression ] )
delay_value ::=
unsigned_number
| real_number
| identifier
These do not express that delay2 and delay3 should be constant expressions,
which generally is expressed in the grammar wherever possible.
delay_value cannot be changed because it is used elsewhere in non-constant
contexts.
I propose to add
constant_delay_value ::=
unsigned_number
| real_number
| parameter_identifier
| specparam_identifier
| genvar_identifier
and change delay_value in delay2 and delay3 to constant_delay_value.
I would have liked to change mintypmax_expression to
constant_mintypmax_expresssion,
but I see that Verilog-XL accepts hierarchical parameter references in delay2
and delay3,
which are not allowed in constant_mintypmax_expression.
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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