Re: Generate proposal

From: Krishna Garlapati (krishna@synplicity.com)
Date: Fri Jan 09 2004 - 17:51:16 PST

  • Next message: Shalom.Bresticker@motorola.com: "Re: Generate proposal"

    >First of all, this is consistent with everything similar in Verilog.
    >You cannot declare an object with the same name as a named behavioral
    >sequential or parallel block, or a module instance, in the same scope.
    >For example, it is illegal to declare
    >
    >
    >
    But isn't it true that the scope of a generate is virtual anyway ??
     From your mention of the $dumpvars
    task, I assume that simulators can treat a generate block like any
    scope in Verilog. Isn't that
    contradictory to the spirit of a generate which only exists until
    elaboration ?? The same argument
    can be made with respect to structures. I also should add here that I
    don't know how simulators handle the
    $dumpvars.

    I have no problem with this restriction, but thought it is non-issue
    since we are not dealing
    with real scopes here.

    >The task force considered not specifying what the standard generated
    >names should be, leaving that implementation-specific. However, that could
    >create incompatibilities between tools, such as making it hard to compare
    >VCD dumps from two different simulators. We also considered going the
    >other direction and allowing these names to be used in hierarchical
    >
    >

    Verification is a big issue too. A standard naming scheme is always
    better than not having one.
    If the user members of the task force did not want names, then so be it.
    Adding block names
    to existing code is much easier than to deal with a global naming
    scheme. But then again, that is
    only my opinion.

    - Krishna.

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