Re: Generate proposal

From: Shalom.Bresticker@motorola.com
Date: Sat Jan 10 2004 - 08:58:50 PST

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    No, the scope of a generate block is real, not virtual.
    It is as real as the scope of a module instance, named block, task, or function.

    Shalom

    On Fri, 9 Jan 2004, Krishna Garlapati wrote:

    > >First of all, this is consistent with everything similar in Verilog.
    > >You cannot declare an object with the same name as a named behavioral
    > >sequential or parallel block, or a module instance, in the same scope.
    > >For example, it is illegal to declare
    > >
    > But isn't it true that the scope of a generate is virtual anyway ??
    > From your mention of the $dumpvars
    > task, I assume that simulators can treat a generate block like any
    > scope in Verilog. Isn't that
    > contradictory to the spirit of a generate which only exists until
    > elaboration ?? The same argument
    > can be made with respect to structures. I also should add here that I
    > don't know how simulators handle the
    > $dumpvars.
    >
    > I have no problem with this restriction, but thought it is non-issue
    > since we are not dealing
    > with real scopes here. 

    -- 
Shalom Bresticker                         Shalom.Bresticker@motorola.com
Design, Verification & Reuse Methodology             Tel: +972 9 9522268
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