Re: Generate proposal

From: Krishna Garlapati (krishna@synplicity.com)
Date: Mon Jan 12 2004 - 15:36:24 PST

  • Next message: Shalom.Bresticker@motorola.com: "Re: Generate proposal"

    I beg to differ. I consider all the stuff within generates are blowed
    off post
    elaboration. The logic that is "created" due to this does not reside in
    a generate
    scope (there is nothing like this post elaboration) but in the scope of
    the containing
    module.

    Thanks,
    - Krishna.

    Shalom.Bresticker@motorola.com wrote:

    >No, the scope of a generate block is real, not virtual.
    >It is as real as the scope of a module instance, named block, task, or function.
    >
    >Shalom
    >
    >
    >On Fri, 9 Jan 2004, Krishna Garlapati wrote:
    >
    >
    >
    >>>First of all, this is consistent with everything similar in Verilog.
    >>>You cannot declare an object with the same name as a named behavioral
    >>>sequential or parallel block, or a module instance, in the same scope.
    >>>For example, it is illegal to declare
    >>>
    >>>
    >>>
    >>But isn't it true that the scope of a generate is virtual anyway ??
    >> From your mention of the $dumpvars
    >>task, I assume that simulators can treat a generate block like any
    >>scope in Verilog. Isn't that
    >>contradictory to the spirit of a generate which only exists until
    >>elaboration ?? The same argument
    >>can be made with respect to structures. I also should add here that I
    >>don't know how simulators handle the
    >>$dumpvars.
    >>
    >>I have no problem with this restriction, but thought it is non-issue
    >>since we are not dealing
    >>with real scopes here.
    >>
    >>
    >
    >
    >

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