From: Shalom.Bresticker@motorola.com
Date: Mon Jan 19 2004 - 08:06:22 PST
>Number: 528
>Notify-List:
>Category: enhancement
>Originator: Steven Sharp
>Environment:
>Description:
Verilog-2001 standard adds $timeskew and $fullskew timing
checks.
SDF standard IEEE Std 1497-2001 does not include these.
It should.
(Any new timing checks proposed for Verilog-2005 should also
be coordinated with IEEE P1497.)
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