Re: New Generate Proposal

From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Fri Feb 06 2004 - 17:44:24 PST

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    The example from 12.4.3 puzzles me. The register declarations
    there are useless, because there's no longer any way to refer
    to them in Verilog itself.

    It seems perfectly reasonable to write something like

       if (do_signed)
          reg signed [0:7] r;
       else
          reg [0:7] r;

       r = ... ;

    but this is no longer possible. Instead, we would have to
    do something like the following -

       if (do_signed) begin : BLK
          reg signed [0:7] r;
       end else begin : BLK
          reg [0:7] r;
       end

       BLK.r = ... ;

    This breaks backward compatibility, and I don't see what it
    buys us.

    -- Brad

        

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