Re: New Generate Proposal

From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Sun Feb 08 2004 - 07:01:29 PST

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    Regarding the uselessness, the code presented is only the skeleton of a real
    case.
    Presumably in a real case, the register declarations would have been followed by

    additional code (within the generate block) which uses them.
    Maybe module instantiations would have been a better example.

    Regarding why the generate block must create a new scope,
    we discussed this at length and the tool implementers convinced me of the
    necessity.
    Steven and Jason can explain it better than I.
    Incidentally, in VHDL, all generate blocks are required to be named.
    And yes, it does break backward compatibility, at least with the 2001 LRM.

    Shalom

    Brad Pierce wrote:

    > The example from 12.4.3 puzzles me. The register declarations
    > there are useless, because there's no longer any way to refer
    > to them in Verilog itself.
    >
    > It seems perfectly reasonable to write something like
    >
    > if (do_signed)
    > reg signed [0:7] r;
    > else
    > reg [0:7] r;
    >
    > r = ... ;
    >
    > but this is no longer possible. Instead, we would have to
    > do something like the following -
    >
    > if (do_signed) begin : BLK
    > reg signed [0:7] r;
    > end else begin : BLK
    > reg [0:7] r;
    > end
    >
    > BLK.r = ... ;
    >
    > This breaks backward compatibility, and I don't see what it
    > buys us.
    >
    > -- Brad 

    --
Shalom Bresticker                           Shalom.Bresticker@motorola.com
Design & Reuse Methodology                             Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd.                    Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL                       Cell: +972 50 441478

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