errata/544: RE: errata/544: Re: errata/544: 15.5, Table 61: does notifier tog gle from X to 0 or to 1?

From: Brophy, Dennis (dennisb@model.com)
Date: Fri Feb 20 2004 - 14:10:00 PST

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    The following reply was made to PR errata/544; it has been noted by GNATS.

    From: "Brophy, Dennis" <dennisb@model.com>
    To: etf-bugs@boyd.com
    Cc:
    Subject: RE: errata/544: Re: errata/544: 15.5, Table 61: does notifier tog
            gle from X to 0 or to 1?
    Date: Fri, 20 Feb 2004 14:21:33 -0800

     I guess it is nice that the opportunity exists for one entity to match XL while the rest of the community must rely on the IEEE work as the standard's official record of behavior.
     
     I understand that these statements are true and an accurate reflection of many Verilog users, but only serve to weaken and tarnish this group and the profession since it only reads to me that the work of this technical group is to a great degree irrelevant.
     
     Maybe all members of the team should be given copies of XL to help in the cause of bringing the LRM into alignment with XL.
     
     -Dennis
     
     -----Original Message-----
     From: owner-etf@boyd.com [mailto:owner-etf@boyd.com]On Behalf Of Steven
     Sharp
     Sent: Tuesday, February 17, 2004 12:20 PM
     To: etf-bugs@boyd.com
     Subject: errata/544: Re: errata/544: 15.5, Table 61: does notifier
     toggle from X to 0 or to 1?
     
     
     The following reply was made to PR errata/544; it has been noted by GNATS.
     
     From: Steven Sharp <sharp@cadence.com>
     To: etf-bugs@boyd.com, Shalom.Bresticker@motorola.com
     Cc:
     Subject: Re: errata/544: 15.5, Table 61: does notifier toggle from X to 0 or to 1?
     Date: Tue, 17 Feb 2004 15:33:47 -0500 (EST)
     
      NC-Verilog started out matching the standard, but was then changed to match
      Verilog-XL. Our users generally consider the second to be more important.
      
      Note that having a notifier toggle from X to 1 means that X is being treated
      like 0, which is consistent with most other such situations in Verilog.
      
      Steven Sharp
      sharp@cadence.com
      

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