errata/345: Re: errata/345: 10.2.1, 10.3.1, 12.3.3, 12.3.4 -- ANSI-style port lists and redeclaration

From: Shalom.Bresticker@motorola.com
Date: Sun Feb 22 2004 - 03:10:00 PST

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    The following reply was made to PR errata/345; it has been noted by GNATS.

    From: Shalom.Bresticker@motorola.com
    To: stefen@boyd.com
    Cc: etf-bugs@boyd.com
    Subject: Re: errata/345: 10.2.1, 10.3.1, 12.3.3, 12.3.4 -- ANSI-style port
     lists and redeclaration
    Date: Sun, 22 Feb 2004 13:15:47 +0200 (IST)

     Stefen,
     
     Please close this issue as a duplicate, as decided by the ETF in the
     last meeting.
     
     Thanks,
     Shalom
     
     
     On Wed, 28 May 2003, Shalom Bresticker wrote:
     
    > I believe this duplicates issues 227 and 233.
    > Also, similar issues are discussed in 292 and 332.
    >
    > Shalom
    >
    >
    > Brad Pierce wrote:
    >
    > > According to 12.3.4, regarding ANSI-style module ports, "Each declared
    > > port provides the complete information about the port." According to
    > > 12.3.3, if a port declaration does not include a net or variable type,
    > > then the port can be again declared in a net or variable declaration."
    > >
    > > Does this mean that the following is legal? --
    > >
    > > module m( input x ) ;
    > > wire x ;
    > > endmodule
    > >
    > > I think it shouldn't be. If the information is complete, then even
    > > redundant declarations should be prohibited.
    > >
    > > Are there any restrictions on redeclarations of ANSI-style
    > > task/function ports? I don't see any restrictions in 10.2.1 and
    > > 10.3.1. To me it would make sense if each ANSI-style task/function
    > > declaration would provide the complete information about the port
    > > and if it would be illegal to redeclare such ports within the body,
    > > even redundantly.
     
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