From: Steven Sharp (sharp@cadence.com)
Date: Tue Feb 24 2004 - 11:10:27 PST
Note that examples like the one in 2.6.2 are not normative. And in this
case, it would have been very easy for leading blanks in the example output
to have been lost during document formatting.
The text in 17.1.1.7 is more of an issue. It is my belief that this text
is simply wrong.
I have traced both sets of text back. The same text appears in the 1995
IEEE standard, the 1993 OVI 2.0 standard, and the Verilog-XL Reference
Manual. This does not match the behavior of Verilog-XL, which prints
leading zero bytes as blanks. The behavior in Verilog-XL appears to be
deliberate, since the %0s format does eliminate the leading blanks for
zero bytes. It seems clear that this was a documentation error in the
XL manual, which has been copied into subsequent specifications.
As Mac notes, this would be consistent with the behavior of other formats,
where leading zeros or spaces are printed unless a 0 appears after the %.
I will file an erratum on this.
Steven Sharp
sharp@cadence.com
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