errata/549: 17.1.1.7 leading zeros in string format

From: sharp@cadence.com
Date: Tue Feb 24 2004 - 11:10:26 PST

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    >Number: 549
    >Notify-List:
    >Category: errata
    >Originator: Steven Sharp
    >Environment:
    >Description:

    The last sentence in 17.1.1.7 says that in string format,
    leading zeros are never printed. This text dates back to
    the original Verilog-XL Reference Manual and has been
    propagated into the current standard. This does not match
    the behavior of Verilog-XL, which prints leading zero bytes
    as blanks. The XL behavior is consistent with the printing
    of other formats, where leading zeros or blanks are printed.
    If a %0s format is used, XL supresses the leading blanks,
    which is again consistent with the description of other
    formats in 17.1.1.3.

    I believe that the intent was to document the behavior of
    Verilog-XL in this situation, but there was an error in the
    original documentation. The standard should be fixed to
    match the intent.

    There is also an example in 2.6.2 that should be changed
    to match. This could be done by changing the example to
    use %0s instead of %s, or by adding 3 spaces to the start
    of the first line of example output.

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