errata/549: Re: errata/549: 17.1.1.7 leading zeros in string format

From: Shalom.Bresticker@motorola.com
Date: Wed Feb 25 2004 - 08:30:00 PST

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    The following reply was made to PR errata/549; it has been noted by GNATS.

    From: Shalom.Bresticker@motorola.com
    To: etf-bugs@boyd.com
    Cc:
    Subject: Re: errata/549: 17.1.1.7 leading zeros in string format
    Date: Wed, 25 Feb 2004 18:42:32 +0200 (IST)

     I think the end of 17.1.1.7 (", and leading zeros are never printed")
     should just be deleted, and a the (correct) description of the behavior
     should go into 17.1.1.3 ("Size of displayed data"), where the
     autosizing is described for the numeric formats, including the
     statement that for decimal formats,
     "leading zeros are suppressed and replaced by spaces.
     In other radices, leading zeros are always displayed."
     This is parallel to what the %s format does.
     
     Also note that the example of 2.6.2 is repeated in 4.2.3,
     except that in 4.2.3 it appears correctly, with leading spaces.
     The difference between the two sections is that 2.6.2 is talking
     about string constants, whereas 4.2.3 is talking about string
     operands.
     
     Probably the proper place of 2.6.1 ("String variable declaration") is in
     Clause 3, and 2.6.2 ("String manipulation") is more or less duplicated by
     4.2.3, which is the proper place for it, anyway.
     
     Shalom
     
     .
    > The last sentence in 17.1.1.7 says that in string format,
    > leading zeros are never printed. This text dates back to
    > the original Verilog-XL Reference Manual and has been
    > propagated into the current standard. This does not match
    > the behavior of Verilog-XL, which prints leading zero bytes
    > as blanks. The XL behavior is consistent with the printing
    > of other formats, where leading zeros or blanks are printed.
    > If a %0s format is used, XL supresses the leading blanks,
    > which is again consistent with the description of other
    > formats in 17.1.1.3.
    >
    > I believe that the intent was to document the behavior of
    > Verilog-XL in this situation, but there was an error in the
    > original documentation. The standard should be fixed to
    > match the intent.
    >
    > There is also an example in 2.6.2 that should be changed
    > to match. This could be done by changing the example to
    > use %0s instead of %s, or by adding 3 spaces to the start
    > of the first line of example output.
     
     --
     Shalom Bresticker Shalom.Bresticker@motorola.com
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