From: Jason Woolf (jasonw@cadence.com)
Date: Tue Apr 06 2004 - 07:54:00 PDT
Yes, we are removing that restriction.
-Jason
> Date: Tue, 06 Apr 2004 15:12:28 +0530
> From: Kausik Datta <kausikd@cal.interrasystems.com>
> To: Francoise Martinolle <fm@cadence.com>
> CC: etf@boyd.com
> Subject: Re: revised comments
> X-pstn-levels: (S:99.90000/99.90000 R:95.9108 P:95.9108 M:96.4018 C:90.6865 )
>
> Hi,
>
> Just one clarification, in IEEE std 1364-2001 Verilog LRM ( Sec
> 12.1.3.1) it was mentioned that if genvar value set to negative that
> will be an error.
> This is not present in the new proposed document.
> Are we removing this restriction on genvar?
>
> Thanks
> Kausik
>
>
> Francoise Martinolle wrote:
>
> > My revised comments taking into account Jason's feedback:
> >
> >
> > Example_12_4_3.v
> > // Example in section 12.4.3
> > module top;
> > parameter genblk2 = 0;
> > genvar i;
> >
> > // generate scope is implicitly named genblk1
> > if (genblk2) reg a; // top.genblk1.a
> > else reg b; // top.genblk1.b
> >
> > // generate scope is implicitly named genblk02 as genblk2 is already a
> > declared identifier
> > if (genblk2) reg a; // top.genblk02.a
> > else reg b; // top.genblk02.b
> >
> > // generate scope would have been named genblk3 but is explicitly named g1
> > for (i = 0; i < 1; i = i + 1) begin : g1 // block name
> > // generate scope is implicitly named genblk1 as the first nested
> > scope inside of g1
> > if (1) reg a; // top.g1[0].genblk1.a
> > end
> >
> > // generate scope is implicitly named genblk4 since it belongs to the
> > fourth generate construct in scope "top" Note that the previous
> > generate construct would have been named genblk3 if it had not been
> > explicitly named g1
> > for (i = 0; i < 1; i = i + 1)
> > // generate scope is implicitly named genblk1 as the first nested
> > scope of genblk4
> > if (1) reg a; // top.genblk4[0].genblk1.a
> >
> > // generate scope is implicitly named genblk5
> > if (1) reg a; // top.genblk5.a
> > endmodule
> >
>
>
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